1. Field of the Invention
The present invention relates to a communication interface circuit; and more particularly, to a communication interface circuit which permits selection of the amount of data converted from serial-to-parallel and from parallel-to-serial.
2. Description of Related Art
FIG. 1 is a schematic block diagram of a codec interface circuit 1 connected to a conventional serial communication interface circuit 2. As shown, the codec interface circuit 1 and the conventional serial communication interface circuit 2 are disposed on different chips which are then connected together. In FIG. 1, a clock divider 20 receives a master clock signal CLK and an initial count setting SET. The clock divider 20 divides the master clock CLK into a plurality of low frequency clocks. In FIG. 1, the symbol phi represents the master clock CLK, but of a different phase.
A clock source selecting unit 30 receives the plurality of clocks output from the clock divider 20, and based on a selection value stored in a register 32 thereof selects and outputs one of the received clocks. By selecting the plurality of received clocks based on a register value, flexibility exists in setting the system speed. Simply by changing the register value, a designer can alter the system speed.
A frame generating unit 34 receives the selected clock SCLK and converts this clock to an even lower frequency clock SYNC. The selected clock SCLK also clocks a transmit unit 36 and a receive unit 38. As shown, the transmit unit 36 receives a write signal and a read signal. The transmit unit 36 is in parallel communication with a data bus, and has a serial output TXout. The amount of serial data transferred between the data bus and the transmit unit 36 is fixed. Conventionally, the width of the parallel data is fixed at either 8 bits or 16 bits. In the conventional serial communication interface circuit 2 of FIG. 1, the width is shown as 16 bits.
The receive unit 38 also receives the read signal, receives parallel communication from the data bus, and has a serial input RXin. Like the transmit unit 36, the width of the parallel communication received by the receive unit 38 is fixed, and is fixed to the same width as the communication between the data bus and the transmit unit 36.
The operation of the transmit unit 36 and the receive unit 38 will be described in detail below with respect to FIGS. 2 and 3. FIGS. 2 and 3 illustrate circuit diagrams of the transmit unit 36 and the receive unit 38, respectively.
A shown in FIG. 2, the transmit unit 36 includes a first transmit shift register TX1 and a second transmit shift register TX2. Both the first and second transmit shifter registers TX1 and TX2 have the same 8 bit storage capacity, receive the selected clock signal SCLK, receive the read signal, and receive the write signal. The first transmit shift register TX1 is connected to the eight most significant bits of the 16 bit wide data bus, and the second transmit shift register TX2 is connected to the eight least significant bits of the 16 bit wide data bus. The serial input of the first transmit shift register TX1 is connected to ground, and the serial input of the second transmit shift register TX2 is connected to the serial output of the first transmit shift register TX1. The serial output of the second transmit shift register TX2 serves as the output of the transmit unit 36. Typically, both the first and second transmit shift registers TX1 and TX2 are composed of eight 1 bit shift registers connected in series.
When a logic high write signal is received, the first and second transmit shift registers TX1 and TX2 input the parallel data on the data bus. Then, with each pulse of the selected clock SCLK, the first and second transmit shift registers TX1 and TX2 serially shift the data stored therein from their serial inputs to their serial outputs. Accordingly, as the eight bits of parallel data are serially shifted out from the first transmit shift register TX1 to the second transmit shift register TX2, logic level low data is shifted into the first transmit shift register TX1 because the serial input thereof is connected to ground. Meanwhile, as the data stored in the second transmit shift register TX2 is shifted out, the serial data from the first transmit shift register TX1 is shifted in. As the shifting of data out of the second transmit shift register TX1 continues, the serial data from the first transmit shift register TX1 is eventually shifted out of the second transmit shift register TX2. After sixteen pulses of the selected clock SCLK, the parallel data originally input by the first and second transmit shift registers TX1 and TX2 is output as serial data.
When the read signal is logic level low, no parallel input or serial output of data takes place. When the first and second transmit shift registers TX1 and TX2 receive a logic high read signal, the data stored therein is output in parallel to the data bus.
Referring to FIG. 3, the receive unit 38 includes a first receive shift register RX1 and a second receive shift register RX2. Both the first and second receive shift registers RX1 and RX2 have the same 8 bit storage capacity, receive the selected clock signal SCLK, and receive the read signal. The first receive shift register RX1 is connected to the eight most significant bits of the 16 bit wide data bus, and the second receive shift register RX2 is connected to the eight least significant bits of the 16 bit wide data bus. The serial input of the second receive shift register RX2 is connected to the serial output of the first receive shift register RX1. The serial input of the first receive shift register RX1 serves as the serial input for the receive unit 38. Both the write enable inputs of the first and second receive shift registers RX1 and RX2 are disabled by being connected to ground. Typically, both the first and second receive shift registers RX1 and RX2 are composed of eight 1 bit shift registers connected in series.
When a logic high read signal is received, the first and second receive shift registers RX1 and RX2 shift data from their serial inputs to their serial outputs in accordance with the selected clock signal SCLK. Because each of the first and second receive shift registers RX1 and RX2 is eight bits wide, it takes eight pulses of the selected clock signal SCLK for data to transfer across one of the first and second receive shift registers RX1 and RX2. After 16 pulses of the selected clock signal SCLK both the first and second receive shift registers RX1 and RX2 are filled with new serial data. Then, the first and second receive shift registers RX1 and RX2 transfer the data stored therein in parallel to the data bus.
The eight bit serial communication interface has the same structure as the 16 bit serial communication interface described above except that the transfer and receive units in the eight bit serial communication interface include a single transmit shift register and a single receive shift register, respectively.
Depending on the design at issue, an operator must select between using an 8 or 16 bit serial communication interface. It is desirable, however, for an operator to be able to use a single interface, and then selectively set the interface to either an 8 bit or 16 bit operating mode. Furthermore, while illustrated as two chips, it would also be preferable in terms of improving integration and improving efficiency to place the codec interface circuit and the serial communication interface circuit on a single chip.